1. Technical Field
The present invention relates to a semiconductor integrated circuit apparatus having an I/O signal line, and more particularly, to a local sense amplifier having an I/O signal line.
2. Related Art
With the increase in integration density of semiconductor integrated circuits, I/O signal lines are hierarchically designed.
For example, DRAM (dynamic random access memory) includes I/O signal lines which are hierarchically divided into global I/O lines GIO, local I/O lines LIO, and segment I/O lines SIO such that signals are transmitted for the respective levels.
A segment I/O line is connected to a bit line to transmit a signal, and is electrically connected to a local I/O line LIO to transmit a signal. Furthermore, the local I/O line LIO is electrically connected to a global I/O line GIO to transmit a signal.
In general, a local sense amplifier includes local I/O lines LIO and segment I/O lines which are alternately arranged with column select signal lines interposed therebetween. Furthermore, an upper local I/O line and an upper segment I/O line are extended to the top portions of the local I/O line and the segment I/O line so as to be secondarily connected to a lower local I/O line and a lower segment I/O line. The upper local I/O line and the upper segment I/O line may be arranged in a direction perpendicular to the lower local I/O line and the lower segment I/O line.
However, as the integration density exponentially increases, the I/O signal lines of the conventional memory apparatus, that is, local I/O lines, segment I/O lines, and column select lines are arranged with a minimum critical dimension (CD) provided therebetween. Since there is a shrinking amount of space to allocate the increasing number of lines, there are difficulties in securing a space for forming a power mesh line.